2 Replies Latest reply on Jan 8, 2017 7:25 AM by kuznar.thomas_1524936

    FX3: Data from FPGA to host is shifted(UVC example)




      I use firmware for FX3 from this topic http://www.cypress.com/forum/usb-known-problems-and-solutions/fx3-firmware-streaming-uvc-data-fpga and for FPGA i use firmware from example AN65974_Designing_with_the_EZ-USB_FX3_Slave_FIFO_Interface.


      I wanted to transmit some data to look in usb device monitor to see what is transferred. I modified the fpga example(pinouts) to my board de2-115(stream_in and loopback examples work fine). FPGA creates data which consist 32-bits of Fs or 32-bits of zeros. The problem is that the first transfer doubles one value in this case zeros and it's looks like this(jpg in attachment). Next transfers make random shifts, once transfer starts with Fs and stays the same for couple of transfers and later starts with zeros(stays in same form for next couple of transfers and returns to its first form. I mean zeros and Fs change their positions). In the stream_in example data from fpga looks always the same like i want.


      Any suggestions how to resolve this problem? Thanks in advance.

        • 1. Re: FX3: Data from FPGA to host is shifted(UVC example)



          Can you please confirm if the Data from the FPGA is coming properly as expected. You can confirm this using the FPGA tools.


          Also, on the FX3 side, please make sure that your flag's watermark values are set properly according to the Application Note specifications. Also, please check if there is any timing delay between the PKTEND, SLWR, and the data lines.




          - Madhu Sudhan

          • 2. Re: FX3: Data from FPGA to host is shifted(UVC example)

            I observed that between one transfer and another there is about 70 clock cycles. I thought that flags "stops" the fpga but i see that during these cycles data in data generator is working and when next transfer starts im losing data that was "made" during these 70 cycles. Signal value increments each clock cycle and at the end of packet the number is 4096, next transfer should start from number 4097 but its 4096+70.(in this case i use fpga example from AN65974).


            I removed FLAGB from FPGA state machine,it changed to 5 clock cycles between transfers. I changed FPGA program and make it wait those 5 cycles and the data that is sent have proper form.