Can you please confirm if the Data from the FPGA is coming properly as expected. You can confirm this using the FPGA tools.
Also, on the FX3 side, please make sure that your flag's watermark values are set properly according to the Application Note specifications. Also, please check if there is any timing delay between the PKTEND, SLWR, and the data lines.
- Madhu Sudhan
I observed that between one transfer and another there is about 70 clock cycles. I thought that flags "stops" the fpga but i see that during these cycles data in data generator is working and when next transfer starts im losing data that was "made" during these 70 cycles. Signal value increments each clock cycle and at the end of packet the number is 4096, next transfer should start from number 4097 but its 4096+70.(in this case i use fpga example from AN65974).
I removed FLAGB from FPGA state machine,it changed to 5 clock cycles between transfers. I changed FPGA program and make it wait those 5 cycles and the data that is sent have proper form.