8 Replies Latest reply on Feb 14, 2017 2:11 AM by nisa

    4 endpoint in slave sync fifo 2 bit

    hr_gnostic_1632581

      hi 

         

      I  have this code for 4 endpoint, but i cant send data from fpga to fx3.

         

      I can send data by an endpoint to fx3 but with another endpoint I cant.

         

      What is the problem?

         

      Can the problem from verilog coding?

         

      In this code i want have 4 endpoint and I want to send data with two channel to fx3. I changed the slavefifosync project.

        • 1. Re: 4 endpoint in slave sync fifo 2 bit
          nisa

          Hi, 

             

          I cannot see your GPIF project. What is the issue that you face while sending the data from the fpga to the FX3? 

             

          When the FPGA is driving the data, can you get if the FX3 is getting the data ? You can check for DMA callback to check when the FX3 recieves one buffer of data. You can also check by using CyU3PGpifGetSMState API to check if the GPIF state machines actually goes in the In_data state to read the data from the FPGA. If the GPIF is not going into In_data state, then the control signals may not be properly asserted by the FPGA. 

             

          First step is to make sure that the GPIF is going tpo the In_data state, else, Fx3 will not receive any data from the FPGA. 

             

          You can refer to AN65974 for the timings and the proper control signals. If you are still not able to identify the cause, please provide us the return of the CyU3PGpifGetSMState and the interface signals at the GPIF. 

          • 2. Re: 4 endpoint in slave sync fifo 2 bit
            hr_gnostic_1632581

            Hi,

               

            Thanks for your reply.

               

            The gpif file is attached.

               

            I can send data by an endpoint and cant send data by two endpoints from fpga to cypress. I dont know how send data from fpga to cypress by 2 endpoints. I dont know how to change the gpif file and verilog code.

            • 3. Re: 4 endpoint in slave sync fifo 2 bit
              nisa

              I understand that you want to send the data from the FPGA -via FX3- to PC through more than one channel. I saw your firmware, where you have created 2 dma channels for read and 2 for data write. That is fine. Next step would be to make the master (FPGA here) to send the data to the FX3 followed by proper control signals. The control signals will ensure that the GPIF state machine is going to the correct (read/write, etc) state and reading/driving the data using the correct socket/thread. In the GPIF project, you will notice that the we are actually doing In_address, which will update the thread address from/to which the data has to be transmitted. So, if the FPGA should be programmed in such a way that the data and address are sampled correctly. If you go through AN65974, you will find the timing for reading and writing from the FX3's fifo. AN65974 also provides the FPGA firmware for data transfer over one read and one write socket. Please check and let us know if you have any doubt related to this. You can use the same FPGA source and modify it as per your requirement as I do not have much expertise on FPGA. If you see any problem related to FX3 side, we can surely assist. 

              • 4. Re: 4 endpoint in slave sync fifo 2 bit
                hr_gnostic_1632581

                Thanks for your reply.

                   

                how I can understand which endpoint send data and i send data with which endpoint?

                   

                and how to select the endpoint in gpif?

                • 5. Re: 4 endpoint in slave sync fifo 2 bit
                  nisa

                  Hi, you cannot exactly select the endpoint from the GPIF side, but you can select the socket of the P-port. the DMA channel has a consumer and a producer field. So, when you create a DMA channel, you will have to enter these 2 fields: P-port socket  and the USB socket (mapped to  endpoints). So, when the data is written into that P-port socket, then the data will be mapped to one particilar EP. Lets take an exaple below:

                     

                  --------------------------------------

                     

                   dmaCfg.prodSckId = CY_U3P_PIB_SOCKET_0;
                      dmaCfg.consSckId = CY_U3P_UIB_SOCKET_CONS_2;
                      dmaCfg.cb = NULL;
                      apiRetStatus = CyU3PDmaChannelCreate (&glChHandleSlFifoPtoU,
                                 CY_U3P_DMA_TYPE_AUTO, &dmaCfg);

                     

                  ---------------------------------------------------------------------

                     

                  Channel is created from P-to-U port. The producer here is PIB socket 0, and consumer is CY_U3P_UIB_SOCKET_CONS_2 (i.e. mapped to EP2. So, when the FPGA write data to PIB-socket 0, then the data is routed to EP2. Similarly, you can create more channels are per your needs. Rest is upto your FPGA code (when to write to which socket, which can be selected by the 2 bit address which is there in the AN65974).

                  • 6. Re: 4 endpoint in slave sync fifo 2 bit
                    hr_gnostic_1632581

                    thanks for reply

                       

                    i attached the firmware with 4 EndPoints. the flagc and flagd is high and flaga and flagb is low in all times. i cant understand the problem. can you help me?

                       

                    this firmware have 4 endpoints ( based on AN65974). i can receive data from EP1 (0x81) and i dont have any data from EP2 (0x82). 

                       

                    what is problem?

                    • 7. Re: 4 endpoint in slave sync fifo 2 bit
                      hr_gnostic_1632581

                      please help me in this issue.

                      • 8. Re: 4 endpoint in slave sync fifo 2 bit
                        nisa

                        I see that you are using thread 0 and thread 2 for P-port to USB channel. The flags will reflect the values of DMA buffer. First ensure that the buffer is available (if the host does not need the buffers data, then it wll get filled and will not be available any further). So, when the buffer is available to be written, then the ready flag will go low. Please make sure that the buffers are empty (hence ready to be written by the master). Also, notice the address lines the FPGA is selecting. I see that you have not used flags for USB-to-P-port communication. I recommend you to use current thread flags (instead of dedicated thread flags). To test, you can discard the buffer in the FX3 firmware if the host is not asking for the data. This way, we make sure that the buffers are available and we can validate the functionality of flags. Also, I recommend you to test once with the AN65974 exact firmware, which will give you the clarity of flag behaviour