Attached is a wave DAC generation project for P4M. The DMA transfer to IDAC on P4 is tricky, it has to be 2 bytes, with MSB set to 0x07, and LSB is actual IDAC value (so RAM array must be 16-bit instead of 8-bit). This MSB is configuration setting for IDAC, controlling current output/bit, which has to be set on each DMA transaction. The DMA trigger has to be set to "unknown width". Max frequency achievable is lower than for PSoC5, reaching ~13.4 kHz @256 points/waveform, but the DAC output quality is better (no bit flipping glitches). Unlike PSoC5, on P4 DMA has no "nrq" signaling the end of Buffer transfer, instead the DMA internal irq and a PinLED are used to for that purpose.
Awesome! Thank you so much!
I have an array of 360 values. Each represents 1 degree of a sine wave. I figured I could create any frequency (0-20KHz) by just increasing the "Clock_DAC" frequency. This doesn't appear to be the case. The maximum output frequency I can create is ~2KHz even as I increase the "Clock_DAC" frequency up to 6 MHz. What's limiting me?
The limiting factor is DMA transfer rate. Setting HFCLK 48 MHz, and using 256 points per waveform, the maximum frequency obtainable was 13.4 kHz, which gives number CPU clocks for single DMA transfer is 48MHz / 13.4 kHz / 256 points = 14 ticks, which is about right for PSoC4. The DMA speed on P4 is slower than on P5 and in this case 2 bytes have to be transferred. To get close to 20 kHz you need to set HFCLK to 48MHz, Clock_DMA to 7MHz, and to reduce amount of waveform points to about 180. Adjusting Clock_DMA using clock divider will give rough granularity on the output frequency at 20kHz limit. You can either vary the number of points per waveform for better control or use some fine control of the DMA clock using DDS: http://www.cypress.com/forum/psoc-community-components/dds24-24-bit-dds-arbitrary-frequency-generator-component http://www.cypress.com/forum/psoc-5-device-programming/psoc-verilog-how-big-design-can-one-make#comment-370296