2 Replies Latest reply on Jan 26, 2017 12:32 AM by RaPi_2071911

    PCB design for CY8C5287AXI-LP095




      I have started PCB design for my custom board for learning PsoC. Since I have not found more appropriate forum division to place my questions please move if necessary to different one. 


      Based on cypress documentation / processor AN and several other sources I have managed to find I have come with initial design which I attached in this post. This is still work in progress but I'm looking forward for your input.


      My design goals included 

      • Have multiple voltage domains ( 1.8V /3V3 and 5V )
      • Have digital and analog split 
      • Be able to choose which voltage is applied to which digital port 
      • Support USB 

      My questions are to the more experienced ones :)

      1. If I have routed the proper connections for powering of the device ?
      3. If I would power VDDIO_1 with 3V3 then I cannot program it with 5V / 
      5. In my plan VDDd will be +5V would that be correct ? 
      7. VDDa will be +5V so here I presume I have made correct choice considering it needs to be equal or greater than other VDDx 



      Thanks a lot for everyone input! 







        • 1. Re: PCB design for CY8C5287AXI-LP095

          Points for schematic after review-


          1)The analog system power voltage, applied to VDDA relative to VSSA, can be up to 5.5 V (absolute maximum), and must be
          greater than or equal to all other applied power voltages. That is, the voltage applied to the other VDDX power pins, relative to
          VSSD, must be ≤ VDDA


          2)The regulator outputs are also routed to pins VCCA and VCCD, respectively.A 1 μF ±10% X5R capacitor must be connected between the respective VCCX and VSSX pins, with as short a trace as possible


          3)The minimum voltage that can be applied to any VDDX power pin is 1.8 V


          4)To reduce power supply noise throughout the device, each VDDX pin should be connected to a 0.1 μF ceramic decoupling


          5)To program using the Port 1 SWD pins (P1[0], P1[1]) and XRES pin (XRES_N or P1[2] as XRES), the host voltage level (VDD_HOST) should be the same as VDDIO1 pin of PSoC 5LP. The remaining PSoC 5LP power supply pins (VDDD, VDDA, VDDIO0, VDDIO2, and VDDIO3) need not be at the same voltage level as the host programmer


          6)For power cycle mode programming, the XRES pin is not required. The VDDD, VDDA, VDDIO0, VDDIO1, VDDIO2, and VDDIO3 pins of PSoC 5LP should be tied together to the same power supply; power to these pins should be toggled to reset the device. Ensure that the programmer used supports power cycle mode. MiniProg3 (rev 7 and later versions) supports power cycle mode




          The above mentioned points answers your all questions.


          For more details look into these documents-

          • 2. Re: PCB design for CY8C5287AXI-LP095

            Thanks ANKS,


            I will now then get to designing the board!