Points for schematic after review-
1)The analog system power voltage, applied to VDDA relative to VSSA, can be up to 5.5 V (absolute maximum), and must be
greater than or equal to all other applied power voltages. That is, the voltage applied to the other VDDX power pins, relative to
VSSD, must be ≤ VDDA
2)The regulator outputs are also routed to pins VCCA and VCCD, respectively.A 1 μF ±10% X5R capacitor must be connected between the respective VCCX and VSSX pins, with as short a trace as possible
3)The minimum voltage that can be applied to any VDDX power pin is 1.8 V
4)To reduce power supply noise throughout the device, each VDDX pin should be connected to a 0.1 μF ceramic decoupling
capacitor
5)To program using the Port 1 SWD pins (P1[0], P1[1]) and XRES pin (XRES_N or P1[2] as XRES), the host voltage level (VDD_HOST) should be the same as VDDIO1 pin of PSoC 5LP. The remaining PSoC 5LP power supply pins (VDDD, VDDA, VDDIO0, VDDIO2, and VDDIO3) need not be at the same voltage level as the host programmer
6)For power cycle mode programming, the XRES pin is not required. The VDDD, VDDA, VDDIO0, VDDIO1, VDDIO2, and VDDIO3 pins of PSoC 5LP should be tied together to the same power supply; power to these pins should be toggled to reset the device. Ensure that the programmer used supports power cycle mode. MiniProg3 (rev 7 and later versions) supports power cycle mode
The above mentioned points answers your all questions.
For more details look into these documents-
http://www.cypress.com/documentation/programming-specifications/psoc-5lp-device-programming-specific...
http://www.cypress.com/file/44581/download
