I am supposed to create a GPIF II state machine on a master FX3 (CYUSB3014) USB Super Speed controller to load a slave device. A transition low to high on CTL0 would latch the data on 32-bit bus into the slave conditioned by a minimum 5ns setup time.
My approach: I use GPIF II Designer for FX3, I/F type is “Master”, Communication type is “Asynchronous”, 32-bit bus, one single control “CTL0”, CTL0 is “Early” and “Toggle”, initially 1 (high).
State machine states: START, IDLE, DATA_CTRL, REMOVE_DATA
In DATA_CTRL “Repeat Count is 1”, Repeat actions until next transition, DR_DATA, DR_GPIO (CTL0). This state (in my opinion and intentions) should last exactly 2 clocks and because CTL0 is “toggle” and initialized to “high”, the first clock CTL0 will be driven low and the second clock will be high, so I generate the low to high transition that will latch DATA on 32 bits into the slave.
In DR_DATA I have “Update new value from data source” checked, data source is “Socket”, Thread number is “Thread0”, and “Remove data from data source” is NOT checked.
In state REMOVE_DATA all user i/f is disabled with the exception of “Remove data from data source”. Of course, I have a DR_DATA action added in this state. My intention here is just to remove source data used in previous state. I expect here to have CTL0 stay untouched (left “HIGH” from the previous state) and after this action state machine should point to next unused data word.
I read all the possible documents but because things don’t work and I have not the optimal electronic means to check, I need advise and/or assurance from somebody more experienced and knowledgeable on the above.
Thank you in advance for your help.
PS. Another question: If in a DR_DATA of a state I have “Remove data from data source” NOT checked, can I combine it with a next state where I have “Update new value from data source” checked and “Remove data from data source” checked and can I be sure that in these 2 states one single data word is actually addressed until removal?