11 Replies Latest reply on Feb 9, 2017 8:02 AM by AnBa_2227836

    How to make .cysch layout for voltage divider of analog input signal

      I have a pressure transducer circuit that outputs a voltage between 0-5V.  There's a pin connected to that output that I connect to analog pin P2[2] on the PSoC 4 board.  I was wondering how to divide this down to meet the 3.3V max VDDA for the ADC SAR Sequencer.  Right now I have my "Transducer" analog input pin connected to the 1st pin of the 12 bit ADC (the 2nd going to ground).  For the divider, I have R1 as 5k and R2 as 10k, connected to the PWR Vdd (all of which is fed to external terminal of the analog pin).  Is this how it's supposed to be connected in the TopDesign.cysch?


      I attached the project bundle.