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1. Yes, VDD_IO and VDD_O are the same.
1. The block diagram in the data sheet shows VDD_IO, but the text in the data sheet references power section VDD_O. Are VDD_O and VDD_IO are the same or is VDD_O a subset of VDD_IO that only includes the GPIO outputs? If so, what do to the inputs do in this mode?
2. In deep sleep mode where current is 1.5 uA, it looks like LPO/32 kHz xtal, IR, PWM and GPIOs are on. I assume the PWM can be programmed to interrupt on expiration. Does the PWM also interrupt the BCM20732 from deep sleep? The data sheet doesnt say anything about interrupts.
3. Do GPIO ports configured as outputs continue to drive in deep sleep?
4. When sending packets periodically for BLE (e.g. 25 ms to 4 seconds), does the BLE stack put the 20732 in 1.5 uA deep sleep mode between the transmissions or is just the sleep mode (20+ uA)?
5. I see a watchdog timer on the block diagram (WDT) but didnt see it described in the data sheet. Is there one?
6. In deep sleep mode, the data sheet says core and base are turned off. Does that mean it loses the RAM contents? If so, where does application software store state information when it goes into deep sleep? The EE or an offboard chip?
7. Wed probably try to use a module, but if using the chip, is a 32k crystal required for BLE or is the 16 khz 128k khz LPO accurate enough?
8. Are there more BLE profiles than those in the data sheet?
2. In 1.5uA deep sleep, the xtal, IR and PWM blocks will be turned off. PWM does not operate in sleep or in deep sleep, and the PWM block is not capable of interrupting or waking up the processor. GPIOs, peripheral uart, IR transmit, Keyscan and quadrature inputs can interrupt/wake the processor.
3. Yes, GPIOs that are output enabled will remain so and drive as configured in sleep/deep sleep.
4. No, when advertising or in connection, the device will not go into deep sleep. However, it will go into other low power modes like sleep and pause based on the connection/ADV interval and other activities. If you want to ADV every few minutes, it is possible to ADV for some seconds, then configure timed wake from deep sleep and then enter deep sleep. After the configured time, the device will be woken up and then the application will be initialized.
5. Yes, there is a watchdog timer and this is configured to go off in 4 seconds. So, if the application spins in a loop forever, the chip will be reset in 4s.
6. Yes, in deep sleep the chip will lose its RAM contents. When woken up, the application will be loaded to RAM from the NV storage and re-initialized. This is very similar to a power-on-reset except that in the case of a wake from deep sleep, some HW state information is retained so that the application can find out what caused the wake.
7. The external 32KHz oscillator is optional. The internal 128KHz LPO is used for sleep and timed wake from deep sleep.
8. WICED Smart SDK comes with source for all the profiles in the ROM along with some more profiles that run from RAM. We may add some more to the SDK in the future. Please look in the SDK for the list of profiles.