3 Replies Latest reply on Mar 9, 2017 2:01 AM by nishanta_46

    FX3 as Quad SPI Master

      I  have a quick question: is it possible to configure the GPIF II Interface in a way that it can read data from a Slave with a Quad SPI interface?

        • 1. Re: FX3 as Quad SPI Master

          As per SPI, During each SPI clock cycle, a full duplex data transmission occurs. The master sends a bit on the MOSI line and the slave reads it, while the slave sends a bit on the MISO line and the master reads it. This sequence is maintained even when only one-directional data transfer is intended.


          The problem when you like to use GPIF is, you can only read or drive data at a time. At one clock, GPIF will either drive the data or read the data. But, as per the SPI requirements, the MOSI and MISO both should be able to transfer data at SCLK. 


          However, you can do it using GPIO. We have an example "UsbSpiGpioMode" where FX3 uses its GPIO to implement SPI: C:\Program Files (x86)\Cypress\EZ-USB FX3 SDK\1.3\firmware\serialif_examples\cyfxusbspigpiomode

          • 2. Re: FX3 as Quad SPI Master

            Thanks for the answer. I don't need to write data to the Slave (no MOSI pin, so no communication from the Master FX3 to the slave).


            I know that technically it's not a "real" SPI interface, but it's compatible. The clock rate is 16 MHz and the Slave clocks out 14 Bit of data (2 Dummy bits and 12 Bit of "real" Data) on 4 to 16 parallel data lines (for the beginning 4 parallel lines are ok) after the #SS signal goes low (see attachment)

            • 3. Re: FX3 as Quad SPI Master

              If you want custom interface, you can do so. As you understand exact SPI is not possible because the GPIF can read or write data at a clock.  


              Another thing to note is: GPIF can be configured for 8 bit (not for 4 bit). So, whenever you do a write to slave data 8 bits will be driven by the GPIF. You can consider the 4 bits. But if you have 1 byte of data in the FX3, in one data write (on one clock), all the 8 bits will go out on 8 data bits (but as you are considering 4 bits only, rest 4 might be ignored).So, the data that has to be sent our needs to be modified accordingly.