6 Replies Latest reply on Feb 22, 2017 8:48 AM by BoTa_264741

PSoC 5LP Custom Verilog Module Creation

userc_38602 Mar 9, 2017 10:38 PM

I am working on psoc cy8c5868axi device. I need a custum verilog module. In the module I want to do, I need to convert 6 parallel data inputs to Serial output. Parallel data entries will not be physically present. I want to do parallel data entry with software or functions.

Please check the picture in the attachment. I draw what I want to design there.

Serial data outputs will work synchronously with clock line. You can think of it like 6 SPI modules that use Single clock line.

I need to prepare a special verilog module for this. But I do not know how to do it. How do I make this work? Is there a document or example you can recommend?

Best Regards

My Module.JPG 45.2 K

1. Re: PSoC 5LP Custom Verilog Module Creation

JoMe_264151 Feb 21, 2017 4:34 AM (in response to userc_38602)

When you installed Creator 4.0 you will find some documentation: Start -> Cypress -> PSoC Creator 4.0 -> Component Development Kit.

There is a "Warp Verilog Guide" and the "Component Author Guide". To ease the construction I would suggest you to use one of the generated verilog files, copy it and change it to your needs.

A simple estimation: Use the UART UDB based files and change it to handle different length.



Bob
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2. Re: PSoC 5LP Custom Verilog Module Creation

userc_38602 Feb 21, 2017 5:22 AM (in response to JoMe_264151)

Hi Bob

Thank you for the reply. Currently I am trying to learn verilog.


A simple estimation: Use the UART UDB based files and change it to handle different length.


How can I get to this example. By changing the SPI module this way, I can make the module I want.
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3. Re: PSoC 5LP Custom Verilog Module Creation

BoTa_264741 Feb 21, 2017 1:45 PM (in response to userc_38602)

Mucit23, There is a component, which ifunctionality is already close to your requirements - ShiftRegister. It converts 32-bit word into serial output stream. You can use DMA to populate Shift register from 4x8-bit sources, e.g. the StatusReg. Evaluate whether your problem can be reduced to 4 inputs. This post lists pretty much all of PSoC Verilog resources available http://www.cypress.com/forum/psoc-5-device-programming/psoc-verilog-how-big-design-can-one-make#comment-370296 Start with simple 8-bit parallel-to-serial verilog example, which can be found on a web, then expand it to 2×8-bit, etc. At some point you may run out of macrocels, as PSoC resources are limited. PS. Since there is no hardware inputs requirement, easiest way would be to transfer data from 8-bit RAM array to 8-bit shift register using DMA, no Verilog necessary.
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4. Re: PSoC 5LP Custom Verilog Module Creation

userc_38602 Feb 22, 2017 12:15 AM (in response to userc_38602)

@odissey1

I try to do simple applications as you say. I basically learned the verilog. I did simple applications with Verilog. There are a few things I do not understand.

I'm just trying to make a simple 8 bit paralel to serial spi module. In this application, How to get data without hardware data entry. I have to do this with a software function. I can do this with DMA in the future. But first, how is it done without DMA? I have to learn this.

Is there a simple spi or shift register for PSOC? Can you help with this?

Best Regards
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5. Re: PSoC 5LP Custom Verilog Module Creation

BoTa_264741 Feb 22, 2017 8:48 AM (in response to userc_38602)
Mucit23,

Attached is basic example of instantiating a Control reg inside Verilog file. More advanced example with API can be found here:

http://www.cypress.com/forum/psoc-community-components/dds24-24-bit-dds-arbitrary-frequency-generator-component



To create an API for register access find its name in the "cyfitter.h" file as shown in the pictures attached.

cyfitter_02_0.PNG 403.2 K

cyfitter_0.PNG 120.1 K

ControlReg_TopDesign_01_0.PNG 47.5 K

ControlReg_Inst_01.cywrk_.Archive01.zip 859.3 K

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6. Re: PSoC 5LP Custom Verilog Module Creation

BoTa_264741 Feb 22, 2017 11:06 AM (in response to userc_38602)

>Is there a simple spi or shift register for PSOC? Cypress stock components have both SPI and Shift register. Note that they created with UDB, not pure Verilog code. The issue is that UDB Datapath can be chained up to 4×8-bit. But you need 6, which I had never seen before. So while playing with Verilog, try to familiarize with existing functionality of SPI and Shift register. Googling "verilog shift register" gave numerous examples of simple code.
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