I have tested with your steps using the firmware in the AN61345 and I have found no issue. Can I know which firmware are you using?
Also, when you mention "cy7c68013a would suddenly fail to transfer data", you mean the EP2 is not taking the data anymore?
In that case is the EP2FF asserted? I have noticed in the description that you mention the status of EP2CS and EP2FIFOFLGS. But can you confirm whether the values of these registers are read when the transfer is failing?
Apart from the one mentioned in the previous post also confirm this:
After last successful transfer happened into EP2(two 512 packets), when the FPGA read the data after few seconds, can you confirm whether the FPGA successfully read the two packets present in the FIFO?
Hi hman ,
Thanks for your comments .
I cant re-produce this problem easily . I used the firmware coming from
AN61345 (FX2LP firmware) but I do minor modification to config slave fifo
to work with external clock , 2x512bytes FIFO , enable EP2EF flag . IFCONFIG
would be set to 0x03 after some time late (FPGA had outputed clock ), and not
triggered by IO pin .
The register's values were read out after EP2 failed to transfer data .
On FPGA side EP2EF flag was valid at that time so FPGA would stop
to fetch data again . I can confirm all datas FPGA read successfully
are the same present in the FIFO .
BTW : After I switch to EP6 with the same config as above , and do the same
test , EP6 would fail to work too . and the register's value are EP6CS = 0x28
EP6FIFOFLGS=0x06 and FPGA detects that EP6EF is valid at that time .
From the register's value , we know there were 2 packets in FIFO . But EF bit
was still set in EP6FIFOFLGS .
If the transfer rate between FX2LP and FPGA is very less compared to the rate at which the Host is sending data to FX2LP then reduce the 'number of XFERs to queue' and 'packets per XFER' (in case of asynchronous transfer) in your Application and see if the issue still exists.