4 Replies Latest reply on Apr 5, 2017 2:31 AM by HemanthR_06

    Help on Cy7c68013A with slave fifo

      Hi all ,


            We are using cy7c68013a with slave fifo to transfer data between FPGA and USB host . All seems


      fine , we could send data by cyconsole correctly to FPGA .  But we find something strange that if FPGA


      do not fetch datas in SLAVE fifo quickly cy7c68013a would fail to transfer data again , at that moment


      we must reset cy7c68013a chip to make it come back to work .  EP2 is configured as Bulk-Out with 2x512-bytes


      FIFOs .  Here is the steps to reoccur this phenomenon . 


             1.  Disable FPGA to fetch data from SLAVE FIFO


             2.  CyConsole sends 3  512-bytes packets to   cy7c68013a , the 3rd packet would fail


             3. Wait for some time . some seconds or some minutes .


             4. Enable FPGA to fetch data again . SLAVE fifo would be cleared .


             5. Try to send packets to cy7c68013a again . 


             6.  Repeat 1 ~ 5 , cy7c68013a would suddenly fail to transfer data .


      I read register EP2CS and EP2FIFOFLGS of cy7c68013a ,  EP2CS = 0x28  and  EP2FIFOFLGS = 0x02 .  FIFOREST could


      not make  EP2CS's value changed .  EP0 still work fine at this time .   It seems EP2 had entered wrong state .


             Anyone knows what is wrong about  cy7c68013a ?  Thanks a lot !

        • 1. Re: Help on Cy7c68013A with slave fifo



          I have tested with your steps using the firmware in the AN61345 and I have found no issue. Can I know which firmware are you using?


          Also, when you mention "cy7c68013a would suddenly fail to transfer data", you mean the EP2 is not taking the data anymore?


          In that case is the EP2FF asserted? I have noticed in the description that you mention the status of EP2CS and EP2FIFOFLGS. But can you confirm whether the values of these registers are read when the transfer is failing?





          • 2. Re: Help on Cy7c68013A with slave fifo



            Apart from the one mentioned in the previous post also confirm this:


            After last successful transfer happened into EP2(two 512 packets), when the FPGA read the data after few seconds, can you confirm whether the FPGA successfully read the two packets present in the FIFO?





            • 3. Re: Help on Cy7c68013A with slave fifo

              Hi hman ,


                   Thanks for your comments .


                   I cant re-produce this problem easily .  I used the firmware coming from


              AN61345 (FX2LP firmware) but I do minor modification to config slave fifo 


              to work with external clock , 2x512bytes FIFO , enable EP2EF flag .  IFCONFIG


              would be set to 0x03 after some time late (FPGA had outputed clock ),  and not


              triggered by IO pin .


                   The register's values were read out after EP2 failed to transfer data . 


              On FPGA side  EP2EF flag was valid at that time so FPGA would stop


              to fetch data again .    I can confirm all datas FPGA read successfully


              are the same present in the FIFO .




                   BTW : After I switch to EP6 with the same config as above , and do the same


              test , EP6 would fail to work too .  and the register's value are EP6CS = 0x28


              EP6FIFOFLGS=0x06  and FPGA detects that EP6EF is valid at that time .


              From the register's value , we know there were 2 packets in FIFO . But EF bit


              was still set in EP6FIFOFLGS .







              • 4. Re: Help on Cy7c68013A with slave fifo



                If the transfer rate between FX2LP and FPGA is very less compared to the rate at which the Host is sending data to FX2LP then reduce the 'number of XFERs to queue' and 'packets per XFER' (in case of asynchronous transfer) in your Application and see if the issue still exists.