3 Replies Latest reply on Mar 26, 2017 11:34 PM by nishanta_46

    Get size of endpoint (FIFO) from the firmware



      I am using FX3 chip with examples from SDK.


      There is callback for U2P transfer. Inside this callback i would like to check if IN endpoint holds any data. In another words is FIFO which is used for IN transfers holds any data. 


      How could i implement that using Cypress FX3 API. 



        • 1. Re: Get size of endpoint (FIFO) from the firmware

          I see you have mentioned U2P transfer. So, The USB will be generating the data and the FX3 will be consuming it, correct? Can you please clarify about your requirement, why you need to check this? What is the size of data where you find this useful? Normally, whenever there is a short packet in the EP, it will be committed and the DMA in the FX3 will get the handle of the data. It can check the size of the data buffer here. 


          If the transactions are in multiple of EP max size, then the host needs to end the transfer using ZLP. ZLP here will indicate the end of transfer, so the handle of the buffer again flows to the DMA. Also, you can ignore to worry about ZLP in U2P transfers if your DMA buffer size is equal to the EP max packet size 

          • 2. Re: Get size of endpoint (FIFO) from the firmware



            Let me explain. The host sends data and the chip generates interrupt to the master. The master writes data back to the chip. It is P2U transfer.


            The problem is that i can;t read the fifo from the host. The callback for P2U transfer is not triggered. So i think there must be problem with my master but to check that i would like to see how much info fifo contain. In U2P transfer callback i would like to check that. Is that possible?

            • 3. Re: Get size of endpoint (FIFO) from the firmware

              Can you check you project step by step to check where you are getting stuck? 


              1) When the host sends data, does the interrupt gets triggered? Can you check and confirm this? 


              2) Once the interrupt gets triggered, is the master recognizing the interrupt signal and moving to write data step? 


              3) If the master tries to writes the data, can you see the clock and relevant control signals getting asserted? 


              4) If all the above is okay, can you check which state the GPIF state machine is going into? Is it going into In_data state and filling up the DMA buffer? 


              5) If the GPIF is going to In_data state, how many in_data does it do? Unless the DMA buffer is completely filled, the DMA callback will not be triggered. If you send a short buffer, then you will have to wrap it up to generate a callback to the firmware which can next commit it to the host.


              It would be better you can share your FX3 firmware+GPIF project as well