FLAGA and FLAGB are used for the Slave FIFO write operation and FLAGC and FLAGD are used for the Slave FIFO read operation.
For write we have Flag A & B. One tell if there is a empty buffer on the DMA side (ready flag), other says if the buffer is about to be full (watermark flag). These are needed for flow control. Similar is the case for read operation where the FPGA tries to read from the slave with the help of flag C&D.
Figure 4 is Synchronous Slave FIFO Write. For write we need to check FLAGA and FLAGB only. So, we have not given the diagram of Flag C&d as we do not care about them during the write sequence.
sorry, I've maken a mistake. FLAGC and FLAGD is not in the Figure 3. Synchronous Slave FIFO Read Sequence
(An65974 , P6) as you described in Table 1. Synchronous Slave FIIFO Interface Signals.
Can I only use FLAGA and FLAGB to design? I'll configure FLAGA to thread0 for Slave FIFO write operation,and configure FLAGB to thread3 for Slave FIFO read operation.For we know the deepth of the Slave FIFO,we can count to be sure when the Slave FIFO is FULL/EMPTY. Is that available？
Yes, you can do so. In the AN65074, we have used two flags per thread because master was not counting the data (but observing the flag status). If you want to count, then it is fine.