All logic in the UDB runs even with the CPU stopped. Think of it as having an additional logic curcuit in addition to the CPU.
When a timer creates in interrupt, it should wake up the CPU though, so it can handle the interrupt.
Hello hli. I am using watch dog timer for reset CPU when it stop. I use 2 funtion:
set up : CyWdtStart(CYWDT_1024_TICKS,CYWDT_LPMODE_NOCHANGE);// WATHDOG_TIME FOR RESET SYSTERM
end reset:CY_WDT_CR_REG = CY_WDT_CR_FEED; // reset watch dog
But I puted funtion :CY_WDT_CR_REG = CY_WDT_CR_FEED in a interrupt (10 ms) on TC of other timer:
CY_WDT_CR_REG = CY_WDT_CR_FEED;
Please Tell me: when CPU stop, watch dog timer do reset CPU or register of watch dog timer do reset?
The WDT circuit asserts a hardware reset to the device after a preprogrammed interval, unless it is periodically serviced in firmware.
The value of the reset status register (RESET_SR0) is read and cleared any time the device is booted.
That value is saved to a global SRAM variable.
The watchdog reset (WRES) and software initiated reset (SRES) sources preserve the RESET_SR0 register. For more information,
refer to the device TRM(page#142) available at these link-