1 Reply Latest reply on Apr 12, 2017 12:16 PM by jpwi

    S6E1C3 latch-up protection

    vandingelen_1580951

      Are there clamping diodes in some of the IOs of the S6E1C3?

         

      According to the datasheet I would expect not... but no explicit mention is made of this.

        • 1. Re: S6E1C3 latch-up protection
          jpwi

          Pin protection devices are on all devices from all manufactures, and are therefor usually not specifically called out. All pins on an integrated CMOS device will have ESD structures, simplified to "clamping diodes".  In order to accommodate higher energy levels, and to protect more sensitive circuit pins, simple clamping diodes have grown into complex structures often with several diodes and a few transistors. Design of this part of the pin I/O circuit depends primarily on the application in which a device is designed for. These structures may connect to a power rail, ground rail, or to some other voltage level within the device as needed for the circuit functionality.

             

          When implementing designs with CMOS integrated devices one can just consider these to be a 0.3V clamping diode, that will prevent voltage greater than the design voltage of the pin from entering the part and creating damage. Once this +0.3V level has been crossed care must be taken to limit the current flow into the pin. This can be done by adding a series resistor between the source and the pin. The ESD structures usually attach to the largest surface area possible to dissipate the heat that this current flow will cause, but eventually EOS (electrical over stress) will occur. Per required industry testing (machine  and human model testing) these structures can withstand 5μW without problems. (just to give you a starting point as to how much you can abuse them)

             

          If your design requires higher voltage or may have things like charged cables plugged into the pins, then external ESD protection should be considered. Such external protection is required as part of the USB specification as cables are almost always used.

             

          Remember two things about these structures:

             

          1) You are allow to exceed the pin clamping voltage if you limit the current. (several clocks work by connecting the AC mains to an interrupt pin for the 50/60Hz timing). In this case a very large resistance is added in series to prevent massive current flow into the pin.

             

          2) Any pin that is connected board to board or board to cable, etc, should be studied for the need to have series limiting resistors to prevent EOS on the pin.

             

          Please consider searching on the internet for "ESD structures in CMOS devices" for additional information.

             

          Hope this helps.