The "Data ready signal" setting configures whether the component alerts when data is ready through either a DMA request signal specific to each channel, or through an interrupt request shared between both channels. Alternatively, the component can also poll the status register to check for new data on the DFB output.
To use the polling method, enable either bit 0 or 1 of Filter_INT_CTRL_REG register, based on the Filter channel selected. This generates an interrupt when data is ready in Filter output registers. Corresponding status bits are set in the Status register. Firmware can poll the corresponding bits in the status register to read the Filter output data.
Filter Status Register:Read this to get the sources of the interrupt. Use the Filter_ClearInterruptSource() macro to clear it.
This register contains five bits indicating the status of block-generated interrupts and three bits of status from the Datapath unit (bits [2:0]).
Thank you very much for your explanation.