2 Replies Latest reply on Feb 2, 2017 2:24 AM by gsns

    Timing parameters CY7C1041GN

    vin_2256051

      Hi,

         

      I am currently performing timing measurements on CY7C1041GN in one of our applications.

         

      According to the datasheet should tACE < 10ns and tDOE < 4.5ns for speed grade 10.

         

      Since their are no requirements on timing between address pin and OE are we toggling this signals simultaneously.

         

      We then get tACE and tDOE = 8.9ns, which is out of spec for tDOE.

         

      Would it be a correct assumption to ignore this since tACE is ok?

         

      Or would it be recommended that we delay the toggling of OE and may get tACE inside the specification this way?

         

       

         

      Best regards

         

      Viktor Nordgren

         

      M.Sc.EE

         

      HMS NETWORKS

        • 1. Re: Timing parameters CY7C1041GN
          gsns

          Hi,

             

          tACE is the time after which SRAM will drive the data out after changing the address keeping all the other control signals active ( CE# low and OE# low).

             

          tDOE is the time after which SRAM will drive the data out  after making OE# low.

             

          Q) Would it be a correct assumption to ignore this since tACE is ok?

             

          A) No you need to meet both tACE and tDOE separately.

             

          Q) Or would it be recommended that we delay the toggling of OE and may get tACE inside the specification this way?

             

          A) As you are changing the address and OE# signals at the same time we recommend you to read the data only after 10ns ( tACE max) so that you can be sure that  SRAM has driven out the correct data.

             

          Thanks,

             

          Krishna.

          • 2. Re: Timing parameters CY7C1041GN
            gsns

            Hi Victor,

               

            Sorry for the Typo in my previous response.

               

            tACE is the time after which SRAM will drive the data out after changing the CE# keeping all the other control signals active ( Address is stable and OE# low).

               

            Thanks,

               

            Krishna.

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