8 Replies Latest reply on Jan 25, 2017 4:36 AM by JoMe_264151

    Are there software interrupts on PSoC4?



      I would like to be able to generate software interrupts, to run code in higher priority.


      Is it possible on PSoC4 (4200M) ?


      I can't use UDB's for this project, so using a Control Register connected to an Interrupt component is not an option.



        • 1. Re: Are there software interrupts on PSoC4?

          There are some ARM M0 internal interrupts, one of them is the SVC (Supervisor Call)


          Excerpt from "Cortex M0 Devices Generic User Guide" from ARM website:


          HardFault A HardFault is an exception that occurs because of an error during
          normal or exception processing. HardFaults have a fixed priority
          of -1, meaning they have higher priority than any exception with
          configurable priority.
          SVCall A supervisor call (SVC) is an exception that is triggered by the
          SVC instruction. In an OS environment, applications can use SVC
          instructions to access OS kernel functions and device drivers.
          PendSV PendSV is an interrupt-driven request for system-level service. In
          an OS environment, use PendSV for context switching when no
          other exception is active.
          SysTick If the device implements the SysTick timer, a SysTick exception
          is an exception the system timer generates when it reaches zero.
          Software can also generate a SysTick exception. In an OS
          environment, the device can use this exception as system tick.





          • 2. Re: Are there software interrupts on PSoC4?

            Are there any examples specifically in PSoC environment?


            How do I implement this in my code?

            • 3. Re: Are there software interrupts on PSoC4?

              #define    PendSVIntNo        14                                //    PendSV  Interrupt Number
              #define    SVCallIntNo        11                                //    Supervisor Call Interrupt Number


              #define PendSVInt(Dummy)    SCB->ICSR = SCB_ICSR_PENDSVSET_Msk                //    This macro will raise a Service Interrupt


              CY_ISR(SuperVisorCall)                            //    Not yet used. SVC normally used to call the system to perform some functions.
              static uint32 CallCount = 0;    


              CY_ISR (PendServiceHandler)




              static void InitializeService(void)
                  NVIC_SetPriority(PendSVIntNo -16,ARTSIntPrio);


              static void InitializeSuperVisorCall(void)
                  NVIC_SetPriority(SVCallIntNo -16,ARTSIntPrio);


              Very basic programming, sorry for that.





              • 4. Re: Are there software interrupts on PSoC4?

                Thanks for your replies.


                I looked at the section you're referring to in ARM UG, and if I understand correctly, an exception has a higher priority than a peripheral interrupt.


                I used to code a bit in TI-RTOS environment (which is of course an OS). It has hardware (peripheral) interrupts and software interrupts. The hardware ones all have higher priority than the software ones. With this distinction you can raise a software interrupt inside a hardware ISR, and it will be handled only after the hardware ISR returns.


                In ARM's exception model, raising an exception will immediately cause the CPU to jump to the exception handler.


                Is there a way to do something similar to TI-RTOS interrupts handling, but without using an RTOS?


                A thought I had just now - raising an interrupt flag of an unused peripheral, and using its ISR as a software interrupt handler. Can this work? How can I implement it (something like putting a component in the design without calling its _Start() function. Or maybe it can be done just by code)?



                • 5. Re: Are there software interrupts on PSoC4?

                  an exception has a higher priority than a peripheral interrupt. Not quite. An exception (apart from being a rock-group) is the same as an interrupt. Arm distinguishes the possible states of interrupts and the state that actually handles (jumps to) the interrupt is named the exception. The priorities are selectable, as you can see I assign in the code snippet priorities (ARTSIntPrio which is not defined here) to interrupts. The Hardware interrupt and the NMI are running at the highest priority (NMI occurs when there is a second HW int during the handling the first one).


                  Question: Why do you want to fire an interrupt and not using critical sections?





                  • 6. Re: Are there software interrupts on PSoC4?

                    I want Hardware interrupts to trigger "software interrupts", that will handle important events immediately, without waiting for their turn in the main loop, and on the other hand to let other hardware interrupts to fire.

                    • 7. Re: Are there software interrupts on PSoC4?
                      • 8. Re: Are there software interrupts on PSoC4?

                        SetPending() needs an interrupt component that must be wired to a hardware signal. So this does not work as a software-only solution.