1 Reply Latest reply on Apr 17, 2017 6:04 AM by nishanta_46

    Problems with the GPIF-II and sync. slave FIFO



      I have some problems with the GPIF-II when implementing a synchronous slave FIFO interface.
      Based on the AN65974 example project I created a firmware for my application. I use auto DMA channels for the data transfer to and from the GPIF. The interface to the FPGA is 32-bit wide, and I use the same flags as in the example.


      The first problem I have is that I run into timing problems when applying a higher clock speed than 60MHz.
      From my understanding I should be able to read a valid data word two clock cycles after setting SLRD and SLOE to low, no matter the clock speed. However, when I operate at higher clock rates there seems to be an additional delay cycle before I can read the correct data. Moreover, when writing data back to the GPIF it seems to sometimes skip a word. Did anyone else notice such a behaviour or does someone have an idea what might cause that?


      The second, and bigger, problem I have is about the I/O voltage level. I got the interface running at 60MHz with the I/O voltage set to 3.3V. I use the FMC interconnect board to connect the FX3 board to the FPGA board. As long as the I/O pins of the FPGA are configured as LVCMOS33 everything works fine. It even works when I disconnect J2 on the FX3 board to set the I/O pins of the FX3 board to 1.8V. However, when I configure the I/O pins of the FPGA as LVCMOS18 the GPIF stops working. The problem now is, that the FPGA board that I have to use for the final design only supports LVCMOS18 at it's FMC I/Os. Does anyone know about this problem and has a possible solution?


      To add some information: I also noticed, that I'm unable to measure a signal from the GPIF pins unless I connect it to the FMC connector of the FPGA board (afterwards I'm able to measure a signal, even when I disconnect it again). When I set a flag to be high by default then I can measure that signal, but the state machine of the GPIF does not seem to work at all. On the other hand, I use two GPIOs (26 and 27) for two special reset signals that I set in the firmware directly, depending on special vendor commands. These signals behave normally, even when the I/Os from the FPGA are set to 1.8V.


      I would appreciate any help I can get, so thanks in advance.



        • 1. Re: Problems with the GPIF-II and sync. slave FIFO

          1) If you have tested AN65974, you must have noticed that we have used a 100MHz interface clock. We have tested this to work fine. Please test AN65974 once if you can. Can you probe the interface signals to show the actual timings/data at your end? 


          2) What do you mean that GPIF stops working? Can you check the voltage levels on the GPIF side/FX3 pins. Please check if you are getting clock, please use CyU3PGpifGetSMState API to check if the GPIF is changing state after getting the clock and signals. 


          3) The FPGA is providing the clock for the GPIF state machine in AN65974, if the FPGA is not connected, then the state machine won't transition. even after clock, the state machine movement is based on control signals from the master. Please clarify which signal you are trying to measure and who is driving the signals? did you make sure that the state machine is running and is in the expected state when you are trying to measure it?