1 Reply Latest reply on Mar 27, 2017 10:10 AM by user_411084576

    Multiple DFFs vs ShiftRegister as delay line on Routed Clock

    bri_2235981

      I have a very simple design (attached).  I'm comparing implementing a shift register (as a delay line) vs a series of DFFs.  The delay line runs off of a routed clock (asynchronous to HFCLK).

         

      The issue I'm having is with shift register component (v2.30).  Using the shift register from a routed clock gives the warning:

         

      Warning: sta.M0021: Design01_timing.html: Warning-1350: Asynchronous path(s) exist from "CyRouted2" to "CyHFCLK". See the timing report for details. (File=<...>\Design01.cydsn\Design01_timing.html)

         

      In addition, the shift register does not work as expected:

         
            
      • When using the routed clock (as is in the attached project):     
                
        • The 2-bit shift register delays the data pulse by ONE clock period (NOT EXPECTED)
        •       
        • The 2 DFFs delay the data pulse by TWO clock periods, as expected
        •      
      •     
      • If I change the routed clock to a New Clock created from HFCLK (NOT as is in the attached project):     
                
        • The 2-bit shift register delays the data pulse by TWO clock periods, as expected
        •       
        • The 2 DFFs delay the data pulse by TWO clock periods, as expected
        •      
      •    
         

      My misunderstanding is in how the ShiftRegister component works.  Specifically, why is it using the HFCLK at all?

         

      Brian