I have a very simple design (attached). I'm comparing implementing a shift register (as a delay line) vs a series of DFFs. The delay line runs off of a routed clock (asynchronous to HFCLK).
The issue I'm having is with shift register component (v2.30). Using the shift register from a routed clock gives the warning:
Warning: sta.M0021: Design01_timing.html: Warning-1350: Asynchronous path(s) exist from "CyRouted2" to "CyHFCLK". See the timing report for details. (File=<...>\Design01.cydsn\Design01_timing.html)
In addition, the shift register does not work as expected:
My misunderstanding is in how the ShiftRegister component works. Specifically, why is it using the HFCLK at all?
I think the Shift register clock will be synchoronized with the bus clock. That will be causing the issue. You may use an sync component may be.