Welcome in the forum, Przemyslaw.
When beginning with PSoCs it will be quite easier when you concentrate on the IDE of Creator. There are datasheets for status and control register components which will be of more interest to you.
Well, I'm afraid that doesn't really answer my question :) Of course, playing with IDE is a good way to gain practical skills, yet I'm asking about purely architectural thing.
I'm quite confident about understanding other aspects of S&C Module (as well as other parts), except for the question stated in my first post. I'm just looking at "Status Register" and "Control Register" component documentation, and it doesn't answer my question, either.
To be more specific about my question - in "PSoC 4100/4200 Family PSoC 4 Architecture TRM":
"188.8.131.52 Parallel Input/Output Mode
In this mode, as Figure 16-36 shows, the status and control routing is connected to the datapath parallel in and parallel out signals. To enable this mode, the SC OUT configuration bits in the UDB CFG22 registers are set to select datapath parallel out. The parallel input connection is always available, but these routing connections are shared with the status register inputs, counter control inputs, and the interrupt output. "
All I'm asking for is an explanation of when such a mode should be used. It seems to me it simply connects parallel in/out to DSI, which is (as far as I understand) possible without this component, so... what's the use?
In general I find the TRM lacking a lot of details, e.g. about DSI internals.
EDIT: I probably misuse DSI name here - what I actually mean is routing resources internal to UDB, I suppose. Is it documented anywhere?
UDBs are configured using HDL, namely Verilog (already installed on your system). In short form there are some cheat-sheets which condense the UDB internals a bit (or byte). Just enter "cheat sheet" into the keyword field at top of this page. The parallel I/O resources of the UDB can be used to construct a Status- or Control register component.
I understand Verilog is used to synthesize UDB config (I have FPGA/Verilog/VHDL background).
Also I've studied "Datapath Configuration Tool Cheat Sheet" document already, if this is the one you're referring to. If you mean any other cheat sheet document, do you mind pointing me to the exact resource? I have no issue understanding Datapath configuration. My issue is about routing resources between Datapath, S&C Module and PLDs.
I believe I have scanned every possible PSoC4 PDF document looking for explanation of "Parallel Input/Output Mode" (as "described" in TRM chapter 184.108.40.206), no luck.
"The parallel I/O resources of the UDB can be used to construct a Status- or Control register component." - could you elaborate?
Let's wait until a Cypress engineer drops in ...
Przemyslaw, You question is rather deep, the best way would be to ask Cypress tech support directly (my Account-> my cases-> file case). In my view it is rather theoretical for PSoC4 processor, which UDB resources are tiny. If you ever decide to make custom UDB component, I would recommend to first develop it using PSoC5, and then port it to P4. Parallel input/output from DSI to Datapath does exist, but I found only few (unofficial) examples so far. It is not common. Once you start tinkering with Creator, I can provide them. Cypress does not encourage components with wide i/o buses, because they eat DSI resources and lower Master clock frequency. DMA transfer is preferred.
Yeah, I'm aware my question is quite deep, indeed. Thanks for tech support suggestion, I'll perhaps give it a try.
In my design I want to transfer 8-bit parallel between datapath and GPIO, I believe it's perfectly doable ("Designing PSoC CreatorTM Components with UDB Datapaths" contains similar example "- Project #5 – Parallel In and Parallel Out"), yet I'd really prefer to understand the limitations better.
It seems that PSoC documentation leans towards "it's as easy as a efw clikcs!" attitude, which is true until you hit some limits you were not aware of :) I'm really used to CPLD / FPGA documentation which typically gives much more detailed info about routing resources.
why there is a need for "parallel output mode" (po[7:0] routed to sc_out[7:0]) ?
Figure 16-29. Status and Control Module in the TRM gives a better picture, so please see sc_out is driven by three different sources :control register,parallel out from datapath ,7 bit counter with only one of them can drive SC_out at a time.So it is left to you if you want to use a control reg/counter /route the datapath parallel output to DSI .(PO Not freely routed to DSI)
Similarly the routing connections sc_in,sc_io_in are shared with the status register inputs, counter control inputs, and the interrupt output and parallel input into the datapath .If you want to use this parallel input into your datapath, you need to make configurations as shown in the example 5 AN82156 at the datapath side .Note that the INT MD and SYNC MD control bits should be cleared to enable SC_IO bits to input mode ,this input goes to status register as well as Parallel input to the datapath.
Example 5 in AN82156 shows the implementation clearly as to how to use parallel out and parallel in .
If you have noticed the example CFB_En is used for dynamic PI /static PI selection means that CFB_En cannot be used for CRC/PRS operation.