Using custom component was the obvious way.
What if you multiplex two SPI components so that 20 bit width can be achieved ? Did you try that possibility? I have not verified this.
You can use a bit lenght of 10 and transfer 2 words (each of which would be stored with 16 bits, with the upper 6 bits unused). Or set 5 bist and transfer 8 bytes (with the upper 3 bits unused for each).
In the end SPI is just a bit stream, and it doesn't care how you divide it into bytes.
I am aware of setting the bit length to four, five and ten bit lengths but run into a command that gets split in two in some cases and that creates a problem when I need to address one function as a whole not in parts. I tried concatenating two variables together and that sort of worked but ran into problems trying to save those functions to eeprom (lost data etc.). There really isn't an easy way around this and was hoping that there was a SPI-Master component in the works that "fixes" this bit length issue. I can create a new component or modify the SPI-Master component since the framework is already there but would need to make the overall data width length to 24/32-bits. What would need to be changed to make it work for an overall width of 24/32 bits? The most obvious would be to add one or two more control and status registers and update the API's and other settings. What else would I need to do to make this happen?
All ideas are most appreciated!!!!
Solution for a custom component always needs verilog.
But as hli pointed out: sending 2 10 bit values will work. What you need to prevent the receiver to see two independent bytes is: Control the ss-line yourself and not by the component. So at begin of a transaction pull the ss-line low and release it when the last bit has been sent (or received, as it is SPI). Regularly, the ss-line is automatically taken high again, when the fifo buffer is empty after transmission of a byte. This might be too early when a remaining byte was not (yet) written to the component.
I fully understand how the SPI Master works and the trickery that is possible with it. I know verilog very well and seriously considering making my own component to finally resolve this issue. I just didn't want to spend gobs of time making a new component, API's, etc. and having to go through all sorts of testing. Setting it up to 2 10-bit values still will not work. Here is a link to the component datasheet:
Pages 18~23 explain the 20-bit registers I need to write to so I can configure the device. 4, 5, 10-bit widths will give me the 20-bit length but run into the problem of having to concatenate variables to make it work which is not desirable. Hope this gives you a better idea of the issues I am facing.
So you have two choices: either create your own verilog component and handle splitting your 20 bits into 3 bytes there. Or use a SPI word length of 4 and do it in your code.
You need to concatenate your bits and bytes somewhere, it just depends where you feel more comfortable doing it. I personally would prefer doing it in C (esp. with splitting 20 bits into 5 times 4 bits its quite easy).
Btw: this chip allows for sending more than 20 bits, then only the last 20 bits are looked at, and the other bits are shifted out on SDO (see page 15). So you can even work with full bytes and just leave the upper 4 bits of the MSB unused. (provided you don't do daisy-chaining - but then you would need more than 20 bits anyway).
Go for Bobs recommendation and control /SS by yourself - otherwise the master might de-assert it during transmission when it has nothing more to send in the TX FIFO.
Thank you guys for the ideas. I figured out a way to do this from what all of you mentioned and without going to the great lengths of creating a new component!!
Glad you got it working!