2 Replies Latest reply on Apr 20, 2018 6:13 PM by user_119654

    PSoC5LP as LIN master?

    user_1269049

      Hi,

         

      can a PSoC5LP be a LIN master? There is a LIN component, but this seems to be a slave only.

         

      The LIN protocol seems to be relatively slow, e.g. 19200bps. Does anyone have experience with LIN and is willing to share?

         

      Best regards,

         

      Turtle

         

      Addition:

         

      In the mean time I found out that there is a component named LIN USART in some PSoC1 that can be used as a LIN master.

         

      As far as I understood is the problem the main problem the synchronisation gap at the beginning that is longer than a byte sent by the UART so that the UART can not generate this signal. Shouldn´t it be possible to use a AND to combine a control register bit and the UART output to generate this sync gap?

         

      I have to send only one constant packet to make one sensor reply.

        • 1. Re: PSoC5LP as LIN master?
          anks

          Presently,we do not have LIN master support in PSOC5LP

          • 2. Re: PSoC5LP as LIN master?
            user_119654

            Turtle,

             

            I agree.  It's definitely not impossible.  I'm thinking of creating a LIN master.  I just haven't started on that journey yet.

             

            I also agree that using combinational logic of a one-shot of 13 bits long and the UART output should do the trick.  However since the bit time of 19.2K is 52us and 13 bits at 677 us, you can use SW control of the output to drive the break pulse and Cypress has a CyDelayUs() which can be set to 677(in us).  If you want to use CyDelay() you can set to 1 (in ms).  Note: The minimum break pulse is 13 bits.  It can be longer if needed.  A full LIN packet is 6.5ms @ 19.2K and the LIN master scheduler @ 10ms leaves 3.5ms to play with.

             

            I just found out the UART (V2.50) has a SendBreak() with a 13 bit setting.  Basically this job is done.  The Sync is just 0x55 and the PID is special in that it only allows 64 IDs because two bits are reserved from special parity operations.   Use LIN Checksum Calculator  to determine the "real" data being sent.  Next, LIN can supply 0 to 8 bytes of data depending on the format of the PID definition.  The last is a simple 8 bit checksum of the data bytes.

             

            One consideration for a proper LIN master is that LIN specifies a +/- 0.5% clock tolerance for the bit rate generator.  This requires an external crystal (<+/-0.1%) or resonator (<+/- 0.4%).  The PSoC internal RC clocks have very good clock tolerances.  Just not good enough for a LIN master.  The "cheat" is if this is not for an automotive product you can loosen the tolerances a little since you can assume the operating temperature is a more narrow range 50F to 80F. 

             

            Len