2 Replies Latest reply on Feb 19, 2017 3:55 PM by BoTa_264741



      The generic family data sheet (e.g. PSoC® 5LP: CY8C52LP Family) indicates


      "5.1 Static RAM ...... Code can be executed at full speed from the portion of SRAM that is located in the code space. This process is slower from SRAM above 0x20000000. ......."


      There does not appear to be specific data sheets for individual devices so it's not clear where the internal SRAM is mapped within the memory space for devices with different size SRAM. I am using a device with 32K SRAM and PSOC creator linker places the RAM so that there is 16K below and above the 0x20000000 boundary, i.e. in two different 32K memory blocks. It places the stack at the top of this region, at 0x20004000.


      My question is: are data accesses also slower to memory above 0x20000000?


      If so can I move my stack below this address? .... there is a control for the stack size but I didn't find one for re-locating the stack in the SRAM.