5 Replies Latest reply on Mar 16, 2017 2:45 PM by BoTa_264741

    larger fifo for shift register



      i am trying to work with a 5Mbit/sec serial input and load it into a cyclic buffer i created in code. later in processing the data is sent over USB.
      My problem is the FIFO depth. the code is just not fast enough to do something useful with the data and come back in time to prevent the  over flow. 


      is there a way to chain fifo's ? would writing in verilog help ?


      (i am using the CY8CKIT-059 PSOC5LP)