Warning: sta.M0019: USB_UART01_timing.html: Warning-1366: Setup time violation found in a path from clock ( CyBUS_CLK ) to clock

[Anonymous]

I run across this problem on some of my PSOC 4 and PSOC 5 designs.  Usually I slightly change the processor clock speed and problem goes away.

   

I am currently trying to setup a clock for 2 ( 32 bit counters ) and a status register.  The value of the timer would be on the order of 1 khz.  I get a setup warning on the clock.  Not sure what the warning is about and not sure how to systematically solve or handle this warning.

[odissey1]

        Timing violation warning indicates that propagation delay of the digital signal may result in phase mismatch. Clicking on the warning opens HTML report with some more detailed information. Usual steps is to reduce system BUS_CLOCK. Other helpful step is to reduce operation temperature in the System tab from -40÷80 to 0÷80.   

[AnkitaS_51]

You can look into this application note  page#29-

   

http://www.cypress.com/file/179056/download

   

And,can also look into this forum post for help-

   

http://www.cypress.com/forum/psoc-4-ble/setup-time-violation-found-path-clock-warning-if-imo-higher-...