clkout = 0;
clkout = 1;
work as you expect in verilog? Or will it generate a glitch pulse?
I am trying to make a very simple design. I have never used Verilog before. I need to generate a clock signal after data is transferred to the output.
I do not know how to do it. Verilog does not work as in C language. what should I do?
I'm not very fit in verilog. A generated pulse will need the provided clock. Set the output at the first LH transition and reset it at the next.
I'm starting to solve the problem.Data output can be made. I just need to generate a clock signal.
But I'm getting an error.
"fit.M0002:'\ParalelToSerial_1:status\'--Can't handle registered multi driver driver"
Why does this error result?
Mucit23, From first glance the verilog code above is unusable. You can find many code examples by googling "SPI verilog code".