This module is a straightforward 8-N-1 UART transmitter, mostly intended for debug trace output. Similar to the standard software transmitter except without hogging the CPU and masking interrupts, but at the cost of a datapath and a bit of routing. The same results may of course be achieved through a full UART component, but being designed for the general case it wastes significant resources on over-sampling, sequencing and easy-of-use.
Admittedly nothing earth-shattering but hopefully useful and working out how to do it without random logic was a bit of puzzle.
Anyway, supply the desired bit-rate on the clock input and tie the FIFO ready status to a spare status register bit or DMA channel. Then poke in FIFO0 with the output characters. Software and a suitable buffering beyond the 4-byte FIFO is application-dependent and left as an exercise to the reader.
Oh, and a single bit-period glitch may be emitted at start-up and is most easily avoided by enabling the output pin late. The signal is already registered so a transparent output will do nicely.
Thank you for posting this 8-N-1 UART transmitter module