4 Replies Latest reply on Apr 18, 2017 3:05 AM by 1065271400_2323246

    GPIF configure

    1065271400_2323246

      hello,everyone,

         

      I have a question about GPIF II, on the left interface configuration ,there is signal configuration ,I think it is data configuration which shows in GPIF is DQ[0:15],how to configure the control signals which shows in GPIF is ctl[0:15],in addition,how to configure the interface with corresponding interface in FX3,for example,I find the PCLK in SCH is 35 of GPIF J6,but when I read previous forum,why someone said the PCLK is GPIO 16?

         

      Please help me ,the very first time use GPIF,

         

      thanks,

         

      regards.  

        • 1. Re: GPIF configure
          nisa

          1) In the GPIF designer when you select the number of input and output signals in the interface definition tab, then the GPIF will automatically assign the CTL pins for these signals. You have some flexibility where you can select the signal and choose the appropriate IO for that CTL pin. You do not need to configure these pins in the firmware, you have to drive them from the GPIF state machine

             

          2) GPIO[16] is the PCLK pin. J6 pin of the BGA package represents GPIO16. Please check the FX3 datasheet-pin description

          • 2. Re: GPIF configure
            1065271400_2323246

            hello,Nishant,

               

            thanks for your time,I understand and I choose the appropriate CTL pin ,but I also want to use the DQ pin same as the CTL pin,because it is bi-directional,can I? Maybe you do not understand me ,so I attached it.Maybe it will waste your time,I am very sorry for it. I want to configure the I/O Matrix according SCH.png,and I have finished partly same as IO matrix.png ,and about DQ[16:31],I have no idea!

               

            thank you !

               

            regards,

               

            Alex

            • 3. Re: GPIF configure
              nisa

              Once you set the GPIF interface(data width, input/output signals), accordingly the DQ pins are set. You cannot drive the DQ pins as a CTL/any other signal. All the DQ bus will be driven at the same time or can be read from at the that time (in_data/dr_data). When you set the number of input and output signal in GPIF, and assign the required IO, the functionality of that pin will also get fixed as output/input. Please let me know if this doesn't answer your question

              • 4. Re: GPIF configure
                1065271400_2323246

                I know,thanks for you patience !Nishant