The state machine timing does not let the state to move to "TH0_RD_LD" because the transition is based on DMA_RDY_TH0 getting asserted, which does not get asserted again by itself. You can check this by creating the scenario till state 7 (dont loop to the next state). This is because the designer doesn't see the DMA_RDY signals getting asserted again, but on real scenario it will (based on whether the host is asking the data). So, if you test on the hardware, you will see the state machine will move to "TH0_RD_LD" once the buffer of thread 0 becomes available again.
I understand what you said,you mean the simulation is not right,but if I test on the FX3 it can work,am I right?I just want to transfer data by it.Thank you !