I've got a design based on AN65974, a Streamer Example with the FX3 in slave mode. On the GPIF side I have an 8-bit synchronous interface with address/data bus multiplexed and FlagA & FlagB used to signal DMA Ready from Thread 0 & Thread 1; Thread 0 handles all IN (input to FX3 from GPIF interface) traffic, Thread 1 handles all OUT (output from FX3 to GPIF interface) traffic. The signals for Flag C and Flag D are not available. On the USB side I have four bulk transfer endpoints, two IN (0x01, 0x02) and two OUT (0x81, 0x82). On the ARM I've set up the DMAs to use automatic transfer with the following mappings:
DMA channel 2 produces a constant stream of traffic, the other DMA channels are very low, sporadic traffic. And you see I'm incrementing the GPIF channels by four since I only have flags available for Thread 0 & Thread 1.
Here's the head-scratcher: If I only create via CyU3PDmaChannelCreate() DMA channels 1 & 2 above, everything works fine - I see a constant stream of traffic on endpoint 0x81. If I create all four DMA channels, the data that was on 0x81 now is on 0x82 and no data is on 0x81. And just for fun, I changed the USB side to use 0x03/Producer 3/0x83/Consumer 3 rather than 0x02/0x82 and saw similar results - all data on 0x83 and no data on 0x81.
What would cause this? Have I messed up something in the address cycle of the GPIF interface? Is there some mapping rule that I've missed? I feel like I've been hitting my head against the wall for a couple days now, and any hint or direction at all would be appreciated.
Found the bug - I was calling CyU3PGpifSocketConfigure() twice.