1 Reply Latest reply on May 18, 2017 2:11 AM by anmn

    How exactly a FIFO works?




      I have a working project with a datapath and two FIFOs. F0 is dynamic and, pretty surprisingly, this advanced mode is clear to me. F1, on the other hand, was configured as static output (F1_INSEL = A1 in the Datapath Configuration Tool). The intended purpose is that the datapath should deposit the value from A1 in a specified state and this value should be transferred to the CPU. Both FIFOs are configured as edge-triggered (FIFO_EDGE = EDGE). And so it works. BUT:


      1. If I don't connect the .f1_load port of the datapath and leave it with its default value, the DMA is not started, which implies that the write request was ignored. But what's the purpose of F1 in A1 WR SRC in the last state (see the attached picture), if, in fact, I can fetch the accumulator value in any state?


      2. If I connect .f1_load as .f1_load(f1_load_strobe), where


          wire f1_load_strobe = (state == STATE_STORE_INPUT);


      the value of A1 is transferred via the DMA to a byte in memory. All the necessary DMA control signals are there, as my scope confirms. But then why I can at all select F0/F1 in the WR section, if it's controlled by an external strobe, anyway?


      Could someone please explain me what's the meaning of the Ax WR SRC fields when configured as F1 or F0? Is it possible to simply write a byte into a FIFO from the datapath and let the insertion magically happen, without any strobes?

        • 1. Re: How exactly a FIFO works?

          Hello Piotr,


          Ax WR SRC in the datapath configuration tool actually determines the contents of the Ax register after ALU operation.If you configured it as F0 or F1,that means Ax register will get the data from F0 or F1. The .f1_load() and .f0_load() is for loading F1 or F1 with data from A0,A1 or output of the ALU. The source is selected by the FxINSEL[1:0] configuration bits. F0 INSEL and F1 INSEL defines the input source for F0 and F1 respectively. If you configure ,F1 INSEL as A1 then  the fifo input will be A1 and the fifo output will be CPU Bus. The default input value for fx_load()  is 1'b0. But the Fx will get loaded based on this input.This input is edge sensitive or level sensitive (controlled by the FIFO EDGE configuration bit). In edge mode,it is sampled at the Datapath clock, and when a ‘0’ to ‘1’ transition is detected a load occurs at the subsequent clock edge. 


          As you mentioned, the .f1_load(f1_load_strobe), where


          wire f1_load_strobe = (state == STATE_STORE_INPUT);


          Whenever the signal f1_load_strobe have a 0’ to ‘1’  transition, the F1 will get loaded with data from A1( since you have selected F1 INSEL as A1)