Ax WR SRC in the datapath configuration tool actually determines the contents of the Ax register after ALU operation.If you configured it as F0 or F1,that means Ax register will get the data from F0 or F1. The .f1_load() and .f0_load() is for loading F1 or F1 with data from A0,A1 or output of the ALU. The source is selected by the FxINSEL[1:0] configuration bits. F0 INSEL and F1 INSEL defines the input source for F0 and F1 respectively. If you configure ,F1 INSEL as A1 then the fifo input will be A1 and the fifo output will be CPU Bus. The default input value for fx_load() is 1'b0. But the Fx will get loaded based on this input.This input is edge sensitive or level sensitive (controlled by the FIFO EDGE configuration bit). In edge mode,it is sampled at the Datapath clock, and when a ‘0’ to ‘1’ transition is detected a load occurs at the subsequent clock edge.
As you mentioned, the .f1_load(f1_load_strobe), where
wire f1_load_strobe = (state == STATE_STORE_INPUT);
Whenever the signal f1_load_strobe have a 0’ to ‘1’ transition, the F1 will get loaded with data from A1( since you have selected F1 INSEL as A1)