Hi Team Cypress,
I'd like to know if you have done any efforts on building an efficient & generic transport + protocol to bridge two psoc cpu's?
Use-case is one or many Analog Coprocessors that needs to interface to a main PSoC, utilizing hw peripherals at a maximum.
I assume the new psoc 6 will need a few similar strategies for IPC communication between the cores. So would be great with a component that can offer an asynchronous event driven machinery between psoc's.
I haven't seen any such work before. May be you can develop your own version according to your requirement. What is preventing you from using standard protocols ? In PSoC 6 being dual core, there should be dedicated hardware for IPC- I am guessing.