1 Reply Latest reply on May 14, 2017 9:23 PM by nisa

    Slave FIFO for stream capture

    claret23_2096031

      Hi-

         

      I'm using Cypress’s EZ-USB® FX3™.

         

      FX3 set up in slave FIFO mode, bulk endpoint (OUT) for stream capture.

         

      DATA FLOW--

         

      FPGA -> FX3 -> HostPC

         

       

         

      Then, I have some problem. 

         

      1. When Host PC start transfer data.(triggering)

         

      2. In spite of FPGA does not send data to FX3, but HostPC capture data. 

         

      It's data only 'EF EF EF EF ....'. 

         

      What's worng with me? and What should i do?

         

       

         

      Thanks!

        • 1. Re: Slave FIFO for stream capture
          nisa

          1) Make sure that the DMA buffers are empty before you start the transfer. It may happen that there are some data lying in the DMA buffer from the previous transfer (Just reset the device and check if you get this the very first time you try to transfer). 

             

          2)If (1) does not help, Please use CyU3PGpifGetSMState API and check the state machine flow. Please make sure that your state machine is not going into in_data state without the FPGA sending the data. Unless the GPIF goes into IN_data, the GPIF will not sample the data from the interface. If the GPIF is going into in_data state, then it may sample something like what you observe. 

             

          3) You can also make the DMA channel manual and see if you get a PROD event. If you get a prod event, even without the FPGA sending the data, then there is something wrong with your interface logic. 

             

          We have an application note to demonstrate slave fifo implementation. Please refer AN65974: http://www.cypress.com/documentation/application-notes/an65974-designing-ez-usb-fx3-slave-fifo-interface