1 Reply Latest reply on Jun 15, 2017 11:34 AM by GeonaP_26

    SImultaneous FIFO load/store




      assume F0 is in dynamic, edge triggered mode and is controlled by UDB, (stores from A0). It contains [1, 2, 3, 4], A0=5. Now, let there be a datapath sequence of states


      PASS A0, (A0 WR SRC = F0)


      ADD A0, A0


      and the FIFO write strobe generates a rising edge when control goes to the ADD. There are two possible scenarios in that state:


      a) F0 = [2, 3, 4, 5], A0 = 1 (read and write were merged: I'd like this to happen)




      b) F0 = [2, 3, 4], A0 = 1 (because: A0 is first written to a full FIFO, so ignored, then the FIFO is read into A0)




      c) undefined.


      Which one will happen? I can check it on a real device, but I don't consider it a proof of anything -- is there a documentation backup for that behavior?


          Best regards,