All signal transitions in EMIF are synchronous to the bus clock on which EMIF works. EMIF_WP_WAIT_STATES and EMIF_RP_WAIT_STATES registers configures the minimum additional wait states for read/write operation depending on the speed of external memory you have configured in the EMIF component. Please refer section 1.3.337 of PSoC5LP registers TRM. The timing diagrams shown in EMIF datasheet shows the signal transitions with timings based on 'T'(Emif clock period). Registers TRM has deails on how many wait states are added for each value of T.