Can you please analyse your control and data lines and verify that the FPGA (or any other device connnected to GPIF) gives the signals with proper timing? i.e, the SLWR starts asserting at 00 and stops at FF? (also check the behavior of the PKTEND signal.
- Madhu Sudhan
ok,thank you ,Madhu Sudhan,I will try it , I just wonder ,now that, the control center can show the right data ,it means my fx3 is right?Because I am not familiar with the FX3 ,I am afraid it is because my fx3 is wrong ,so I want to confirm it ,thank you !
Whatever be the buffers committed in the FX3 to the USB, the same is displayed in the control center. So, if proper data is not displayed on the control center, we need to analyse the data path right from the FPGA -> GPIF (and state machine) -> DMA Buffers and Commit.