3 Replies Latest reply on May 23, 2017 4:53 PM by user_342122993

    ADC input mux select by UDB again

    piotr.wyderski_2406846

      Hello,

         

      the situation gets weirder and weirder. TRM (page 398, chapter 38.2.1) says:

         

      The input selection, both positive and negative, is made through the
      input selection mux, which can be controlled through either
      the SAR routing registers in the analog interface or through
      the UDB. Setting the SARx_CSR[4] bit takes the positive
      input through UDB and clearing the bit takes the positive
      input through registers. Similarly, setting the SARx_CSR[3]
      bit takes the negative input through UDB and clearing the bit
      takes the negative input through registers.

         

      So there is the attached project which attempts to do exactly that. It compiles with a bunch of warnings, e.g.

         

          Warning: Can't find signal in jack map: Net_39_3

         

      or:

         

         Warning: Signal Net_39_0: No path found from Net_39_0:macrocell.q to SAR_1.vn_ctl_udb_0

         

      I don't see anything obviously wrong with the (not very sensible) project, so what's going on?