That sounds like something that would be easy to test physically. From our own testing, the chip will draw power if it is trying to startup, but if it entered shutdown voluntarily through the software, then it might not draw current (no idea).
Thank you for replying.
I understand...but how can I realise this in PSOC software and how to measure? That is confusing to me. When the Enable pin in voltage regulator is below 0.4 V then it put the regulator in shutdown mode and draws only 18nA. But my VBAT is connected to PSOC and after the sgutdown, will the PSOC still draws current from VBAt? To test that how can I proceed. I just want to test but I do not have volatge regulator with me. I only want to test this with PSOC and battery. How do I can achieve it.
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Here is a document which contains the low power modes for the PSoC 4 chip: http://www.cypress.com/documentation/application-notes/an86233-psoc-4-low-power-modes-and-power-reduction-techniques
If you have a current meter, then you can cut/jump traces to place the current meter between the PSoC and the battery. The PSoC will draw a minute amount of current whenever it is connected, but if it enters "Shutdown" mode, then the power draw becomes almost non-existent.
To test this, try programming the PSoC to do the different power modes (peripherals/pins/hardware functions being on/off will affect power draw too)
sleep, deep-sleep, hibernate, shutdown will all have different power draws; Placing an amp/current meter between the battery and PSoC will let you measure the current while it is in the power mode. Ex: Program a PSoC project that enters CySysPmStop() as soon as it starts, then measure the power draw from the amp-meter to see how much current is being drawn from the battery when it is in the shutdown mode. Repeat for the other three to get power-draw for the different modes. Keep in mind that adding peripherals running while the PSoC is in each mode can affect the power draw to the point where the power mode has little effect on the result.
I did what you said and measured the currents in stop and hibernate mode. But it gives me way high current.
Stop Mode: 0.24 mA
Hibernate mode: 0.26 mA
I am confused because I read in the data sheet that for Stop Mode it need 60 nA and for Hibernate mode 150 nA,
How to get these current consumption in PSOC?
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Remove debug capabilities by setting the debug mode to "GPIO" in Creator system view. This will save a lot of current.
Thanks I was able to reduce the current after changing setting the debug mode to "GPIO" in Creator system view and got
Stop Mode: 54 uA
Hibernate Mode: 54 uA
Is it possible to get in nA range by any other changes further?
Assuming you don't need the PSoC to wake up, you can turn off clocks/peripherals and other hardware to drop the current to the levels they show;
The "Current Consumption" is the minimum power consumption, as adding more active hardware will draw more current.
Do you have any components in the "Top Level Design.cysch"? If you have some enabled, they could be drawing current. Try doing a sleep/power-off call to the peripherals/hardware that you want to turn off before going to Stop/Hibernate.
Double check that all GPIO pins you have connected to the PSoC are set to HIGH-Z to remove any leakage currents. Also, turning off clocks before going to Stop/Hibernate might help (Afaik, they should be disabled upon entering the power mode automatically for Stop/Hibernate modes)
(The lowest current draw I achieved with our project was 2 uA, being able to wakeup from deep-sleep on a button push (3 buttons))
I am using example code hibernate and code. I am not sure what changes I have to do in this to reduce the current consumption. I tried everything.
Am I using correct example for testing my query?
And I am also confused that how can I shut off PSOC and then add battery to one of the ADC pin of PSOC and check how much current its drawing?
Any help would be really nice.
Please find the attachment.
Note: you are leaving the LEDs powered/running, which may or may not be active/drawing power while the chip is hibernated/stopped;
To achieve lower power:
Disable the LEDs by setting them to OFF, or set the drive modes to HIGH IMPEDANCE (ANALOG is the mode I think)
Put the UART component into sleep mode by calling UART_Sleep();
I've reattached the project with the modifications that I would make to reduce current draw.
For testing the actual power draw, I would either hook up a very small resistance in series with the battery, and measure the voltage drop to determine current draw (too large will cause the chip to never start due to low voltage input, so be aware of proper electrical requirements for powering the PSoC)
Or, you can hook up your current meter in series with the battery, and merely leave it measuring/connected while you start/run/stop/hibernate the PSoC while observing the current values.
Here is an AN that explains it more fully for measuring battery/power usage: http://www.cypress.com/documentation/application-notes/an92584-designing-low-power-and-estimating-battery-life-ble
Thaks man...I tried and it worked and got current in range of 100-150 nA.
You're Welcome! I'm glad it is working