I am working on interfacing of Cyclone V GX with FX3 using HSMC. I was referring the application note AN65974 provided by Cypress for my work. Now I am stuck with the Pin mapping on FPGA, as the pin info provided on the HSMC board and HW schematic (CYUSB3ACC-006) is pretty confusing.
For example, the DQ0 is told to configure for HSMC connector pin number J1-88, but when I took at the schematic of Cyclone V GX its mentioned pin 88 of HSMC is connected to VCC12_HSMC, which I cannot assign for. Similarly, for many of the pin info provided on HSMC I have a similar issue. So I decided to map with the pins of Altera Cyclone III Starter Kit (FPGA used in Application note: AN65974 ) by referring the schematic. I have configured the pins on Cyclone V GX and tried to run the STREAM IN example provided by the Cypress. Unfortunately, I could see there are some issues with some pin configuration. As I could see the received counter value is not in sequence, after looking at the received counter values, I could see there are some problems with few pins. Now I don't understand, what is correct pin configuration for Cyclone V GX to communicate with FX3 via HSMC? As I did get proper info in HSMC HW schematic document (630-60197-01_CYUSB3ACC-006_HSMC_INTERCONNECT_BOARD_SCHEMATIC.pdf).
I am attaching schematics of Cyclone V GX , Altera Cyclone III (3C25 FPGA used in application note AN65974 ) and configured Pins planner info of Cyclone V GX FPGA. Could someone please help me regarding this? I couldn't able to proceed further because of this issue.
Thanks in advance!