2 Replies Latest reply on Jun 9, 2017 1:37 AM by artemykhaustovgd_2271321

    Slave FIFO with Altera Cyclone III starter board (AN65974)

    artemykhaustovgd_2271321

      Hello.
      I try to organize Slave FIFO Interface with CYUSB3KIT-003, CYUSB3ACC-006 HSMC Interconnect Board and Altera Cyclone III Starter Board as described in AN65974.
      I've compared pinout of CYUSB3ACC-006 with Altera's Starter Board pinout -- and it doesn't match. Some signals from CYUSB3KIT-003, which is needed for Slave FIFO Interface, don't reach FPGA. For example, signal FLAGA. In GPIF II Interface it is CTL[4] (picture 1). CTL[4] on CYUSB3ACC-006 HSMC Interconnect Board attach to pin №100 (picture 2). But on Altera's Starter Board pin №100 connects to 12V and doesn't reach FPGA (picture 3).
      So, I don't understand, how Slave FIFO Interface can work? Maybe I miss something. 
      Look forward to hearing from you. Thanks.

         

      Pic 1 from "CYUSB3014 EZ USB FX3 datasheet", page 32.
      Pic 2 from "630-60197-01_CYUSB3ACC-006_HSMC_INTERCONNECT_BOARD_SCHEMATIC", page 3.
      Pic 3 from "cycloneiii_sb_3c25", page 11.