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PLLM is the lower 6-bits of RCC->PLLCFGR
The BCM43362WCD4 module has a 26MHz external crystal.
The STM32F205xx supports up to 120MHz clock frequency.
The default PLL setting for WICED SDK looks incorrect.
In this case, PLL48CK will be 49.92[MHz] and SYSCLK will be 124.8[MHz].
Is my understanding correct?
If yes, please check whether PLLM can be changed from 25 to 26?
From the text you posted, the lower 6-bits = 0x1a = 26
So, PLLM is already set to 26.
Please see the setup in the following file around line 268 (and copied below)
/* Use the clock configuration utility from ST to calculate these values
RCC_PLLConfig( RCC_PLLSource_HSE, 26, 240, 2, 5 ); /* NOTE: The CPU Clock Frequency is independently defined in platform.h */
RCC_PLLCmd( ENABLE );