2 Replies Latest reply on Jul 13, 2017 8:59 PM by jie.song_1918886

    GPIF II Timing in Synchronous Mode - FPGA Timing Constaints

    kov023

      Hey Guys,

         

      I have a Cypress FX 3 USB host connected to a Spartan 6 FPGA. I am using the GPIF 32bit interface to connect to it running in Synchronous mode.

         

      I am running the interface at the maximum frequency of 100Mhz. 

         

      I am not sure if i have got the timing constraints correct on the FPGA side.

         

      I have drawn it out in the attached "GPIF Timing Diagram Mod". Basically this is what i think it should be, but i would like some confirmation from someone else that i am on the right track.

         

      If there are additional constraints that you think i should add, please advise.

         

      The timing constraints that I’ve specified in the UCF file is as follows:

         

      ##-------------------------  GPIF timing Constraints  -------------------------------##

         

      # Offset constraints

         

      # Timing group for pads

         

      TIMEGRP "DQ" = PADS("DQ<0>") PADS("DQ<1>") PADS("DQ<2>") PADS("DQ<3>") PADS("DQ<4>") PADS("DQ<5>") PADS("DQ<6>") PADS("DQ<7>") PADS("DQ<8>") PADS("DQ<9>") PADS("DQ<10>") PADS("DQ<11>") PADS("DQ<12>") PADS("DQ<13>") PADS("DQ<14>") PADS("DQ<15>") PADS("DQ<16>") PADS("DQ<17>") PADS("DQ<18>") PADS("DQ<19>") PADS("DQ<20>") PADS("DQ<21>") PADS("DQ<22>") PADS("DQ<23>") PADS("DQ<24>") PADS("DQ<25>") PADS("DQ<26>") PADS("DQ<27>") PADS("DQ<28>") PADS("DQ<29>") PADS("DQ<30>") PADS("DQ<31>");

         

      # Offset in (for Cypress FX3 -> FPGA)

         

      TIMEGRP "DQ" OFFSET = IN 5ns VALID 7.5ns BEFORE "SYSCLK_P" RISING;