I need a 3mbps UART, but I also want to run my PSoC5 at 64MHz. This creates a conflict, because a 3mbps UART needs either a 24MHz or a 48MHz clock, and so I can't use a 64MHz master clock. (It's a shame I can't get access to the 48MHz USB clock).
One way around this would be to create a 4/3 or 8/3 clock divider. I've looked online, but can't find any examples of how to do this. Does anyone know if it's possible to do such a thing in Verilog?
Many thanks - Hugo