4 Replies Latest reply on Jun 4, 2017 6:18 PM by etsl_2357181

    Sine Wave LUT to DAC example

      I am trying out example 3 from the application note "Getting started with DMA" (AN52705). It says that the frequency of my output should be the clock speed triggering my DMA divided by the number of entries in my LUT. My LUT has 128 entries and the output wave frequency responds as expected until it reaches about 15KHz. At that point no matter what the frequency of the output wave remains at about 15-16KHz.


      Any idea why this might not be working?

        • 1. Re: Sine Wave LUT to DAC example
                  Triggered DMA consumes approx. 14 BUS_CLK ticks per single transfer. Max output frequency achievable: BUS_CLK / Table_size / 14 ~ 15khz @ 48MHz CPU. Above that limit DMA cycles get skipped and coherency is lost. Only solution is to reduce table size and increase bus clock.   
          • 2. Re: Sine Wave LUT to DAC example

            This is kind of what I suspected. Do you know where I can read more about the bus cycles needed to do the DMA transfers? I couldn't find anything in the datasheet linked from the DMA module or the app-note.


            To increase the clock I set PLL_OUT, MASTER_CLK, and BUS_CLK (CPU) to 75MHz. Just an arbitrarily high value a little below the CPU freq of 80MHz (I'm using the CY8C5888LTI-LP097) and the new maximum frequency of 36-40kHz follows your math. But I am not getting the error "Warning-1366: Setup time violation found in a path from clock ( CyBUS_CLK ) to clock ( CyBUS_CLK )" and in the timing report, it seems to say that the maximum frequency of the CyBUS_CLK is 47.495MHz?


            Thanks for the help, just trying to understand it all :)

            • 3. Re: Sine Wave LUT to DAC example

              One way to improve frequency range is to set operating temperature range from -40÷85C to 0÷85C in System tab of the Design Wide Resources.


              Timing violation warning indicates that propagation delay of the digital signal may result in phase mismatch. If project is not critical, it is still possible to run it with timing setup violation (some imperfections may arise). This app note covers tricks to resolve timing issues




              Look into PSoC5 TRM (section 6.  PHUB and DMAC) for DMA clocks consumption. Help->Documentation->PSoC technical reference manuals-> PSoC® 5LP Architecture TRM.pdf




              For higher frequencies you can use hardware generated sine (no DMA involved). See e.g:






              P.S. The above formula stays correct. Using 66MHz clock I see ~18 kHz sine output (256 samples/period), and with some tricks ~21.4 kHz. If it is still relevant, you can post your project for review (File->Create Archive Bundle->minimal) 

              • 4. Re: Sine Wave LUT to DAC example

                I was on here asking a new question and saw that you updated your answer. I got it working to where I needed it, and your suggestions helped a great deal. thanks!