The register USB_SIE_EP1_CR0 could be used to STALL the end point and clear the end point. If the 7th bit of the register is set, this STALL the end point. If the 7th bit is cleared, this could clear the STALL. Could you please refer the below link, page no 744, to get more information about this register: http://www.cypress.com/file/136211/download
Thanks ANKS, that is exactly what I had failed to find in the documentation.