You may use SPIM_STS_SPI_IDLE
SPI IDLE: Set when the SPI Master state machine is in the IDLE State. This is the default state after the component starts. It is also the next state after SPI Done. IDLE is still set until Tx FIFO Not Empty status has been detected.
Bob, my point is that the SPI Master state machine does not know anything about buffer content, so relying on SPI_DONE of SPI_IDLE implies that interrupt process runs perfectly, timely and with no misses. May be SPI_IDLE fits "the best that can be done". That said, I will use SPI_IDLE.