Is it happening in the same locations for every 32K sample size i.e always first four locations or last four locations are missing or is it random ?
Can you please us send us your code for review.
Thankyou for the prompt reply. Data missing in every 32k samples is in fixed fashion.4 words(each 32 bit) missing at the end of each 32k blocks. VHDL code for fifo interface is attached for your reference.In the code we are writing and reading incrementing pattern from 00 to FF.The data(binary format) which read through the checkout is also attached.Here data is missing in bytes (32k-15)86f1 to 86FF(32k-1) and this pattern is repeating after every 8700 bytes(32K).
We would be grateful if you could look into the matter as early as possible and solve the issue. This is urgently required to move ahead with our testing.
We have contacted our product team regarding the issue. We will review the code ,debug and get back to you as soon as possible.