1 Reply Latest reply on Jul 24, 2017 4:05 AM by srdr

    EZUSB3-AN65974-DDR

    neurotek_2082096

      Hi there, I am interfacing an Altera DE1 board to ezusb3 and have been looking through the vhdl documentation for the slaveFIFO2bstream_out.vhd (down load is AN65974). I notice that a mega function for DDR is included as a component. Initially I thought this was just used to double the frequency from 50MHZ to 100MHZ, but after simulation I see that the PLL component doubles clock frequency. The only thing that i can see the DDR do is change the phase of the output clock. Is this megafunction necessary to interface with the EZUSB3 (for stream out to slave fifo) or is it a remnant of a previous architecture from a more complicated design?

         

       download of sample code: http://www.cypress.com/documentation/application-notes/an65974-designing-ez-usb-fx3-slave-fifo-interface