Did you disabled the SWD functionality of the SWD pins on the System tab?
There's an appnote about power saving on PSoC4 devices, that one might help you (i can't find it right now).
Yes the SWD pin function is set to "GPIO", so it is disabled. Also, as you can read in my post, I was trying out that appnote about powersaving. As I said, the only difference is 5V vs 3.3V.
I just ran into the same behavior with my CY8CKIT-042-BLE kit (tried 2 separate kits).
- Power jumper on 5V setting results in ~110 uA DeepSleep current.
- Power jumper on 3.3V setting results in ~1.5 uA DeepSleep current.
I did unplug the module and power it directly without the BLE baseboard and observed that I got the 1.5 uA sleep current with 3.3V or 5V supply. Same thing if I reattach the module to the baseboard but remove the power jumper and supply my own power to pin 1 of J15 (BLE_VDD). So clearly something on the VDD side of that jumper is leaking at 5V.
So the good news is the chip itself seems to be behaving correctly but the kit baseboard has some sort of leakage with 5V supply.
I don't know what is causing this, I did a quick review of the kit base-board schematic and didn't see anything jump out at me. Would be nice if anyone (Cypress) knows of a fix/workaround.
Sorry for not checking back but I also got some results from earlier. They match dsweet's, that is, if the BLE module is not powered from the base board, then the consumption is alright even with 5V (1.6uA). So the Pioneer base board is at fault here, at least partially, read on.
I tried to analyze what is wrong on the baseboard, and arrived at the following conclusion:
It has to do with the protection circuit of the F-RAM and possibly also with the PSoC4 chip. What happens is that first the module board is powered from 3.3V, and so C29 charges up. Now when you switch to 5V, the protection circuit will turn off VFRAM, but will not shunt it to the ground. So VFRAM stays floating, but is actually holding a potential due to the charged capacitors. This apparently causes a high leakage current on pin P5_0/P5_1, though I'm not yet sure where this current is flowing to. The leakage current decreases to "only" 90uA if you just write "1" to the pins (and zero leak if "0" is output), so I guess it is a float issue. The leakage also stops if you disconnect both P5_0 and P5_1.
- You can only observe this issue if C29 is charged before switching to 5V. For example you won't be able to reproduce the issue if you are turning on the board to 5V after a long off-state. You need to power it from 3.3V, then from 5V.
- Even if VFRAM is floating, this shouldn't cause any of the P5_x pins to leak, since they are all set to analog HiZ. I thought my module might be faulty, but since there are others experiencing the same issue, this might be a more generic module defect. Please Cypress, check this.
- The best way to completely stop the leakage on the Pioneer board is to make sure VFRAM is discharged when powering from 5V. You can do this manually by shorting C29's poles, or automatically by outputing a logic "0" on P5_0 or P5_1.
The issue might also have to do with the working of the protection circuit, because if I measure the resistance on the unmounted R7 when running from 5V (which means - and I checked this by measuring the gate - Q6 is turned off), I measure a resistance of only 110KOhms. This is way too low. Again, I thought my board could be faulty, but it'd be best if others checked this too just to make sure this is not a board design issue.
I hope Cypress can clear things up even more, but I think I could offer some help. Anyway, to other Pioneer users, here is a warning:
Read and understand the above if you are trying to measure sleep current with J16 set to 5V. Otherwise your measurements could well be bogus.