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WICED Studio Wi-Fi Combo

Anonymous
Not applicable
[WICED-SDK-2.2.1]

The BCM43362WCD4 module has a 26MHz external crystal.

The STM32F205xx supports up to 120MHz clock frequency.

The default PLL setting for WICED SDK looks incorrect.

RCC->CFGR: 0x0000940a

RCC->PLLCFGR: 0x05403c1a

In this case, PLL48CK will be 49.92[MHz] and SYSCLK will be 124.8[MHz].

Is my understanding correct?

If yes, please check whether PLLM can be changed from 25 to 26?
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1 Solution
Anonymous
Not applicable
PLLM is the lower 6-bits of RCC->PLLCFGR

From the text you posted, the lower 6-bits = 0x1a = 26

So, PLLM is already set to 26.

Please see the setup in the following file around line 268 (and copied below)

<WICED-SDK>/Wiced/Platform/common/ARM_Cortex_M3/STM32F2XX/stm32fxx_platform.c

....

/* Use the clock configuration utility from ST to calculate these values

* http://www.st.com/internet/com/SOFTWARE_RESOURCES/TOOL/CONFIGURATION_UTILITY/stm32f2xx_clockconfig.z...

*/

RCC_PLLConfig( RCC_PLLSource_HSE, 26, 240, 2, 5 ); /* NOTE: The CPU Clock Frequency is independently defined in platform.h */

RCC_PLLCmd( ENABLE );

....

View solution in original post

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1 Reply
Anonymous
Not applicable
PLLM is the lower 6-bits of RCC->PLLCFGR

From the text you posted, the lower 6-bits = 0x1a = 26

So, PLLM is already set to 26.

Please see the setup in the following file around line 268 (and copied below)

<WICED-SDK>/Wiced/Platform/common/ARM_Cortex_M3/STM32F2XX/stm32fxx_platform.c

....

/* Use the clock configuration utility from ST to calculate these values

* http://www.st.com/internet/com/SOFTWARE_RESOURCES/TOOL/CONFIGURATION_UTILITY/stm32f2xx_clockconfig.z...

*/

RCC_PLLConfig( RCC_PLLSource_HSE, 26, 240, 2, 5 ); /* NOTE: The CPU Clock Frequency is independently defined in platform.h */

RCC_PLLCmd( ENABLE );

....

View solution in original post

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